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CMX639 consumer / commercial cvsd digital voice codec ? 2000 consumer microcircuits limited d/639/2 november 2000 provisional issue features applications single chip full duplex cvsd codec integrated input and output filters consumer and business handheld devices robust coding for wireless links digital voice appliances programmable sampling clocks spread spectrum wireless 3 and 4 bit companding algorithms cordless phones low power/small size for portable devices voice recording and storage 1.9ma/2.75ma typ. @ 3.0v/5.0 v delay lines 3.0v to 5.5v operation time domain scramblers powersave mode multiplexers and switches 1.1 brief description the CMX639 is a continuously variable slope delta modulation (cvsd) full duplex codec for use in consumer and commercial digital voice communication systems. with its robust and selectable coding algorithms, low cost, very low power, and small size, the CMX639 is ide al for use in a wide variety of consumer and business digital voice applications. its completely integrated codec simplifies design and eliminates the costs, complexity and risk of external filters and software algorithms. 8kbps to 128kbps data/sampling clock rates are supported both via external clock signals or internally generated, programmable clocks. internal data/sampling clocks are derived from an on - chip reference oscillator that uses an external clock crystal. an internal data/sampling clock ou tput signal is provided to synchronize external circuits, if desired. multiplexer applications are also well supported by the encoder output?s three - state/high impedance enable feature. the CMX639 operates from 2.7v to 5.5v supplies and is available in the following packages: 24 - pin tssop (CMX639e2), 16 - pin soic (CMX639d4) and 22 - pin pdip (CMX639p6).
cvsd codec CMX639 ? 2000 consumer microcircuits limited 2 CMX639/2 contents section page 1.0 features and applications ................................ ................................ .. 1 1.1 brief description ................................ ................................ .................. 1 1.2 block diagram ................................ ................................ ...................... 3 1.3 signal list ................................ ................................ ............................ 4 1.4 external components ................................ ................................ .......... 6 1.5 general description ................................ ................................ ............. 7 1.6 application notes ................................ ................................ ................ 7 1.7 performance specification ................................ ................................ .. 8 1.7.1 electrical performance ................................ ............................... 8 1.7.2 packaging ................................ ................................ ............... 15
cvsd codec CMX639 ? 2000 consumer microcircuits limited 3 CMX639/2 1.2 block diagram figure 1 block diagram
cvsd codec CMX639 ? 2000 consumer microcircuits limited 4 CMX639/2 1.3 signal list p6 22 - pin pdip e2 24 - pin tssop d4 16 - pin soic signal name type description 1 1 1 xtal/clock input input to the clock oscillator inverter. a 1.024mhz xtal input or externally derived clock is injected here. 2 n/c no connection 2 3 2 xtal output the 1.024 mhz output of the clock oscillator inverter. 3 4 n/c no connection 4 5 3 encoder data clock input/ output a logic i/o port. external encode clock input or int ernal data clock output. clock frequency is dependent upon clock mode 1 and 2 inputs and xtal frequency. note: no internal pull - up is provided. see table 3. 5 6 4 encoder output output the encoder digital output. this is a three - state output whose condition is set by the data enable and powersave inputs. see table 2. 6 7 not present idle force encoder input when this pin is at a logical '0' the encoder is forced to an idle state and the encoder digital output is ?0101??, a perfect idle p attern. when this pin is a logical '1' the encoder encodes as normal. internal 1m w pull - up. 7 8 5 data enable input data is made available at the encoder output pin by control of this input. see encoder output pin. internal 1 m w pull - up. 8 9 n/c no connection 9 10 6 v bias normally at v dd /2, this pin should be externally decoupled by capacitor c4. internally pulled to v ss when powersave is a logical '0'. 10 11 7 encoder input input the analog signal input. internally biased at v dd /2, this input requires an external coupling capacitor. the source impedance driving the coupling capacitor should be less than 1k w . a lower driving source impedance will reduce encoder output channel noise levels. 11 12 8 v ss power negative supply 12 13 n/c no connection 13 14 9 decoder output output the recovered analog signal is output at this pin. it is the buffered output of a lowpass filter and requires external components. during ?powersave? this output is open circuit. 14 15 n/c no connectio n
cvsd codec CMX639 ? 2000 consumer microcircuits limited 5 CMX639/2 p6 22 - pin pdip e2 24 - pin tssop d4 16 - pin soic signal name type description 15 16 10 powersave input a logic '0' at this pin puts most parts of the codec into a quiescent, non - operational state. when at a logical '1', the codec operates normally. internal 1 m w pull - up. 17 n/c no connection 16 18 not present idle force decoder input a logic '0' at this pin gates a ?0101...? pattern internally to the decoder so that the decoder output goes to v dd /2. when this pin is a logical '1' t he decoder operates as normal. internal 1m w pull - up. 17 19 11 decoder input input the received digital signal input. internal 1 m w pull - up. 18 20 12 decoder data clock input/ output a logic i/o port. external decode clock input or internal data clock output. clock frequency is dependent upon clock mode 1 and 2 inputs and xtal frequency. note: no internal pull - up is provided. see table 3. 19 21 13 algorithm input a logic '1' at this pin sets this device for a 3 - bit companding algorithm. a logical ' 0' sets a 4 - bit companding algorithm. internal 1 m w pull - up. 20 21 22 23 14 15 clock mode 2 clock mode 1 input input clock rates refer to f = 1.024mhz xtal/clock input. during internal operation the data clock frequencies are available at these ports for external circuit synchronization. independent or common data rate inputs to encode and decode data clock ports may be employed in the external clocks mode. internal 1m w pull - ups. see table 3. 22 24 16 v dd power positive supply. a single 3. 0v to 5.5v supply is required. this pin should be externally decoupled to v ss by capacitor c5.
cvsd codec CMX639 ? 2000 consumer microcircuits limited 6 CMX639/2 1.4 external components figure 2 recommended external connections r1 note 1 1m w 10% c4 note 4 1.0 m f 20% c1 note 2 33pf 20% c5 note 5 1.0 m f 20% c2 note 2 33pf 20% x1 note 6, 7 1.024mhz c3 note 3 1.0 m f 20% table 1 recommended external components notes: 1. oscillator inverter bias resister 2. xtal circuit load capacitor 3. the drive source impedance c onnected to the coupling capacitor?s input node, rather than the CMX639 encoder input pin node, should be should be less than 1k w . output idle channel noise levels will improve with even lower source impedances driving the coupling capacitor?s input node. 4. bias decoupling capacitor 5. v dd decoupling capacitor 6. a 1.024mhz xtal/clock input will yield exactly 16kbps/32kbps/64kbps internally generated data clock rates 7. for best results, a crystal oscillator design should drive the clock inverter input with signal l evels of at least 40% of v dd , peak to peak. tuning fork crystals generally cannot meet this requirement. to obtain crystal oscillator design assistance, please consult your crystal manufacturer.
cvsd codec CMX639 ? 2000 consumer microcircuits limited 7 CMX639/2 1.5 general description data enable powersave encoder output 1 1 enable 0 don't care high z (open circuit) 1 0 v ss table 2 encoder output clock mode 1 clock mode 2 data/sampling clock rate (clock/xtal = f = 1.024mhz) example for f = 1.024mhz 0 0 external clocks external clocks 0 1 internally generated @ f/16 internally generated @ 64kbps 1 0 internally generated @ f/32 internally generated @ 32kbps 1 1 internally generated @ f/64 internally generated @ 16kbps table 3 clock modes and pins 1.6 application notes figure 3 system configuration using the CMX639
cvsd codec CMX639 ? 2000 consumer microcircuits limited 8 CMX639/2 1.7 performance specification 1.7.1 electrical performance 1.7.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (v dd - v ss ) - 0.3 7.0 v voltage on any pin to v ss - 0.3 v dd + 0.3 v current into or out of v dd and v ss pins - 30 +30 ma current into or out of any other pin - 20 +20 ma p6 package min. max. units total allowable power dissipation at tamb = 25c 800 mw ... derating 10 mw/c storage temperature - 40 +125 c operating temperatur e - 40 +85 c e2 package min. max. units total allowable power dissipation at tamb = 25c 300 mw ... derating 3.0 mw/c storage temperature - 40 +125 c operating temperature - 40 +85 c d4 package min. max. units total allowable power dissipation at tamb = 25c 800 mw ... derating 10 mw/c storage temperature - 40 +125 c operating temperature - 40 +85 c 1.7.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max . units supply (v dd - v ss ) 2.7 5.5 v operating temperature - 40 +85 c xtal frequency 0.500 2.048 mhz
cvsd codec CMX639 ? 2000 consumer microcircuits limited 9 CMX639/2 1.7.1.3 operating characteristics for the following conditions unless otherwise specified: xtal frequency = 1.024 mhz, sample clock rate = 32 kbps, audio test frequency = 820 hz, v dd = 3.0v to 5.5v, tamb = - 40c to +85c, audio level 0db ref (0dbm0) = 489mv rms. static values notes min. typ. max. units i dd (powersaved) 6 600 m a i dd (enabled) @ v dd = 3.0v 6 1.90 ma i dd (enabled) @ v dd = 5.0v 6 2.75 ma input logic ?1? 70% v dd v input logic ?0? 30% v dd v output logic ?1? 80% v dd v output logic ?0? 20% v dd v digital input impedance logic i/o pins 1.0 m w logic input pins, pull - up resistor 1 300 k w digital output impedance 4.0 k w analog input impedance 2 100 k w analog output impedance 800 w three state output leakage 4 m a insertion loss 3 0 db
cvsd codec CMX639 ? 2000 consumer microcircuits limited 10 CMX639/2 dynamic values notes min. typ. max. units encoder: analog signal input levels v dd = 3.0v 7 - 37 6 db v dd = 5.0v 7 - 33 10 db principal integrator frequency 160 hz encoder passband 4 3240 hz compand time constant 5 ms decoder: analog signal output levels v dd = 3.0v 7 - 37 6 db v dd = 5.0v 7 - 33 10 db decoder passband 4 3200 hz encoder decoder (full codec): passband 4 300 3400 hz stopband 6 10 khz stopband attenuation 60 db passband gain 0 db passband ripple - 3.0 3.0 db output noise (input short circuit) 8 - 60 dbm0p perfect idl e channel noise (encode forced) 8, 9 - 63 dbm0p group delay distortion 5 (1000hz - 2600hz) 450 m s (600hz - 2800hz) 750 m s (500hz - 3000hz) 1500 m s xtal/clock frequency 10, 11 0.500 1.024 2.048 mhz notes: 1. all logic inputs except encoder and decoder data clocks. 2. the source impedance driving the coupling capacitor should be less than 1k w . a lower driving source impedance will reduce encoder output channel noise levels. 3. for an encoder/decoder combination. 4. see figure 5. 5. group delay distortion for the full codec is relative to the delay with an 820hz, - 20db signal at the encoder input. 6. not including any current drawn from the device pins by external circuits. 7. recommended values. 8. dbm0p units are measured after the application of a psophometrically weighted filter that is commonly applied in voice communication applications per ccitt recommendation g.223. 9. forced idle encode/decode control not available on d4 (16 - pin soic) package. 10. some applications may benefit from the use of an xtal/clock frequency other than 1.024mhz. note: codec time constants and filter response curves are effectively proportional to xtal/clock frequency
cvsd codec CMX639 ? 2000 consumer microcircuits limited 11 CMX639/2 and so will shift with the use of xtal/clock frequencies other than 1.024mhz. for example, the specified encoder decoder (full codec) passband of 300hz min. to 3400hz max. for a 1.024mhz xtal/clock will shift to 600hz min. to 6800hz max. when the device is operated from a 2.048mhz xtal/clock. for this reason, all CMX639 codecs involved in the same commu nications link should usually be operated from the same xtal/clock frequency. example 1: a design saves the cost of a 1.024mhz xtal or clock generator by making use of an already existing clock source of a frequency other than 1.024mhz. example 2: best noise performance is achieved when the CMX639 codec data clock is internally generated. if a codec bit rate other than 16kbps, 32kbps or 64kbps is desired then an xtal/clock different from 1.024mhz can be used to proportionately shift the available set of internally generated clock rates, as needed. example 3: to increase the codec high frequency response and audio bandwidth a faster xtal/clock speed can be used. other designs may prefer the proportionately higher codec bandwidths and data rates that can be supported with faster clock speeds. 11. in general, optimum codec performance is achieved when both encoder and decoder xtal/clock signals are synchronized. while this is practical in many telecom applications, it may not be so for others such as wireless data links. the CMX639 decoder can generally deliver best performance when its data clock is recovered/derived from the received data stream and applied as an external data clock to the decoder as per the decoder timing depicted in figure 4. nonetheless, some xtal/clock frequency and data rate combinations are better served by the use of internal clocks. experimentation with each specific design may provide the best guidance for making this design choice.
cvsd codec CMX639 ? 2000 consumer microcircuits limited 12 CMX639/2 1.7.1.3 operating characteristics (continued) timing diagram encoder timing decoder timing multiplexing function encoder clock encoder data output decoder clock decoder data input encoder output data enable high z high z data true time data clocked data clocked t if t ir t cl t ch t ch t su t h t dr t pco t df figure 4 serial bus timing for the following conditions unless otherwise specified: xtal frequency = 1.024 mhz, v dd = 3.0v to 5.0v, tamb = - 40c to +85c. serial bus timing (ref. figure 4) notes min. typ. max. units t ch clock 1 pulse width 1.0 m s t cl clock 0 pulse width 1.0 m s t ir clock rise time 0 100 ns t if clock fall time 100 ns t su data set - up time 450 ns t h data hold time 600 ns t su +t h data true time 1.5 m s t pco clock to output delay time 750 ns t dr data rise time 100 ns t df data fall time 100 ns
cvsd codec CMX639 ? 2000 consumer microcircuits limited 13 CMX639/2 1.7.1.3 operating characteristics (continued) typical codec performance 0 -10 -20 -30 input level = -15dbmo data clocks = 32kbps xtal = 1.024mhz 1 2 3 4 5 6 frequency (khz) -40 -50 -60 c o d e c g a i n i n c l u d i n g e n c o d e a n d d e c o d e , ( d b ) figure 5 typical frequency response (32kbps) frequency (hz) s / n ( d b ) 35 30 25 20 15 10 5 500 1000 1500 2000 2500 3000 3500 input level = -20db 64kb/s 32kb/s 16kb/s figure 6 typical s/n ratio with input frequency
cvsd codec CMX639 ? 2000 consumer microcircuits limited 14 CMX639/2 input frequency = 820hz input level (dbmo) 3 2 1 0 -1 -40 -30 -20 -10 0 10 a t t e n u a t i o n ( d b ) r e f @ - 1 5 d b m o figure 7 typical variation of gain with input level (32kbps) s / n ( d b ) input level (db) ref. -40 -30 -20 -10 0 ref: 0db input level = 489mvrms input frequency = 820 hz 64 kbps 32 kbps 16 kbps 10 20 30 35 figure 8 typical s/n ratio with input level
cvsd codec CMX639 ? 2000 consumer microcircuits limited 15 CMX639/2 1.7.2 packaging figure 9 p6 mechanical outline: order as part no. CMX639p6 figu re 10 e2 mechanical outline: order as part no. CMX639e2
cvsd codec CMX639 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro - static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily perfor med. oval park - langford maldon - essex cm9 6wg - england telephone: +44 (0)1621 875500 telefax: +44 (0)1621 875600 e - mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk figure 9 d4 mechanical outline: order as part no. CMX639d4
cml product data in the process of creating a more global image, the three standard product semiconductor companies of cml microsystems plc (consumer microcircuits limited (uk), mx-com, inc (usa) and cml microcircuits (singapore) pte ltd) have undergone name changes and, whilst maintaining their separate new names (cml microcircuits (uk) ltd, cml microcircuits (usa) inc and cml microcircuits (singapore) pte ltd ), now operate under the single title cml micro- circuits . these companies are all 100% owned operating companies of the cml microsystems plc group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. cml microcircuits product prefix codes until the latter part of 1996, the differentiator between products manufactured and sold from mxcom, inc. and consumer microcircuits limited were denoted by the prefixes mx and fx respectively. these products use the same silicon etc. and today still carry the same prefixes. in the latter part of 1996, both companies adopted the common prefix: cmx. this notification is relevant product information to which it is attached. company contact information is as below: cml microcircuits (uk)ltd communication semiconductors cml microcircuits communication semiconductors cml microcircuits (singapore)pteltd communication semiconductors cml microcircuits (usa) inc. communication semiconductors oval park, langford, maldon, essex, cm9 6wg, england tel: +44 (0)1621 875500 fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com 4800 bethania station road, winston-salem, nc 27105, usa tel: +1 336 744 5050, 0800 638 5577 fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com no 2 kallang pudding road, 09-05/ 06 mactech industrial building, singapore 349307 tel: +65 7450426 fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com d/cml (d)/1 february 2002

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